Some examples of architectures with serial high speed I/O lanes include the serial advanced technology attachment (SATA), universal serial bus (USB), and peripheral component interconnect express (PCI-Express or PCIe), among others. The PCI-Express interconnect architecture enables components and devices from different vendors to inter-operate in an open architecture. This architecture spans multiple market segments, from clients to servers. The PCIe uses numerous lanes for communication between components, and operates according to a PCIe specification. The PCI-Express Specification states that the Electrical Idle differential peak output voltage per lane (VTX-IDLE-DIFF-AC-p) is not to exceed 20 mv (p-p). However, if all the lanes of a specific configuration enter or exit an idle state simultaneously, the differential peak can be large, exceeding this limit. As PCIe compliant computing systems continue to increase the number of communication lanes, the problem becomes more challenging. As the PCIe lanes shrink to 22 nm and below, the differential peak can exceed 20 mV if all the lanes enter or exit an idle state simultaneously, which may damage the end card circuits. This phenomenon is observed from actual simulations. Approaches for maintaining the differential peak within the specification, such as adding large capacitors on board lanes to absorb the differential current, are not sufficient for interconnects with larger numbers of lanes, and where the technology has shrunk to 22 nm and below.
Further, as more functionality, like PCIe, gets integrated into processors, it becomes increasingly difficult to replicate errors found in the post debug cycle. Periodic System Management Interrupt (PSMI) technology is some help with this issue. However, PSMI works with deterministic protocols, and PCI-Express is not deterministic. Rather, PCI-Express includes non-deterministic elements such as flow control, Low-Power states, and speed change built into the specification.